1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method. In particular, the invention relates to a data processing apparatus including plural processors, and a data processing method used therefor.
2. Description of Related Art
In recent years, a chip prepared by mounting plural processor core modules, a peripheral RAM, and a peripheral functional module on one LSI chip has come into widespread use. Further, along with the advanced functionality, the above processor core module incorporates a program cache memory in many cases. Providing the program cache memory that operates at higher speeds than general RAMs increases a processing speed of the processor. Japanese Unexamined Patent Application Publication No. H11-306029 discloses an interrupting method that issues an interruption request to the processor having a cache memory. With this method, a program for executing an interruption processing is transferred from a main memory to the cache memory at a predicted timing.
Incidentally, the simplest solution to a problem of how to run a program code that is beyond a program memory capacity of the processor is to increase the program memory capacity of the processor or a size of the peripheral RAM.
Meanwhile, there is a demand for the LSI chip to reduce a size of an installed processor core or RAM from the viewpoints of yield and packaging area. In addition, the processor core module to be installed is provided as a reusable part. Thus, it is difficult for development of processor cores to change a program memory capacity from one LSI chip to another in the light of cost.
Against this background, required is a technique of executing a program code that is beyond an internal program memory capacity without changing the hardware configuration such as increasing the program memory capacity. That is, in some data processing apparatuses having a processor, it is desired that the internal program memory capacity be smaller than that of the program to be executed.
Referring to FIG. 12, the system configuration of a conventional data processing apparatus having plural processors is described. FIG. 12 is a block diagram of the system configuration of the conventional data processing apparatus. The system is composed of a processor (1) 600, a processor (2) 620, and an external RAM 650. The processor (1) 600 and the external RAM 650 are connected through a memory bus, and the processor (2) 620 and the external RAM 650 are connected through a memory bus. The processor (2) 620 can send an interruption signal 640 to the processor (1) 600.
The processor (1) 600 includes an internal program memory 613 for storing a program, and a program cache memory 612 for storing a program code that is fetched through program fetch access to the external RAM 650. A memory controller 611 controls a process of writing/reading a program code to/from the program cache memory 612, the internal program memory 613, and the external RAM 650. An arithmetic logical unit 610 controls a memory controller to read the program code stored in the internal program memory 613 or the like and execute a program.
The processor (2) 620 includes an internal program memory 632 for storing a program. A memory controller 631 controls a process of writing/reading a program code to/from the internal program memory 632 and the external RAM 650. An arithmetic logical unit 630 controls a memory controller 631 to read the program code stored in the internal program memory 632 or the like and execute a program.
FIG. 13 shows a memory map of the processor (1) 600 and the processor (2) 620. The external RAM 650 is mapped to the memory map of each of the processor (1) 600 and the processor (2) 620. That is, an external RAM 700 is mapped to the processor (1) memory map, and an external RAM 711 is mapped to the processor (2) memory map. Thus, the processor (1) 600 and the processor (2) 620 can arbitrarily read/write data or the like to/from the external RAM 650. In addition, the processor (2) program code that is beyond the capacity of the internal program memory 613 of the processor (1) 600 is stored in a processor (1) program code table data 710 mapped to the memory map of the processor (2) 620.
Referring to FIG. 11, an operation of a general program cache memory is described. FIG. 11 shows the configuration of the program cache memory. When the processor executes a program fetch access to the external RAM 650, a hardware component automatically copies the fetched program code to one of program cache memory areas 510, 511, 512, and 513. During the coping operation, the fetched program code and adjacent program codes are collectively copied by L bytes. Simultaneously, a hardware component records which address of an external RAM a program code is copied from, with respect to program cache memory tags 530 to 533 which manages a memory area 500 as a copy destination.
FIGS. 14 and 15 are flowcharts of a conventional program. FIG. 14 is a flowchart of an operation of the processor (1) 600, and FIG. 15 is a flowchart of an operation of the processor (2) 620. First, the processor (2) 620 starts copying program codes (codes that are beyond the capacity of the internal program memory 613 of the processor (1) out of the processor (1) program codes) to the external RAM 711 (step S811). In this way, the external RAM 650 stores the above program codes. After the completion of copying a program code (table data 710), the processor (2) 620 notifies the processor (1) 600 of the completion of writing the program code (table data 710) by using the interruption signal 640 (step S812). The processor (1) 600 waits for the interruption signal 640 to input in step 801, and is shifted to a normal program execution state as a result of the signal input (step 802). After that, if the processor (1) 600 executes the program codes on the external RAM 650, the executed program codes are sequentially copied to the program cache memory 612 from an external RAM 650 through the hardware operation.
In the related art, the external RAM 650 stores the program codes that would overflow the internal program memory 613 of the processor (1). As a result, there arises a problem in that the external RAM 650 cannot be used for other purposes, and another RAM should be added for the other purposes. This problem is caused as follows.
Unless all of the processor (1) program codes stored in the external RAM 650 are copied to the processor (1) program cache memory 612, there is a possibility that the processor (1) memory controller 611 executes a fetch access. Thus, data stored in the external RAM 650 cannot be rewritten in order not to damage the processor (1) program code. Here, the processor (1) 600 needs to completely execute the program codes on the external RAM 650 for copying all of the stored data from the external RAM 650 to the processor (1) program cache memory 612. That is, it is necessary to read all of the program codes that cannot be stored in the internal program memory 613, and write the read codes to the program cache memory 612.
However, it is conceivable that there are infrequently-executed program codes in view of a conditional branching structure of general program codes, and the execution conditions. Thus, it is difficult to determine whether or not the processor (1) 600 completely executes the program codes. That is, it is difficult to determine whether or not all the program codes on the external RAM 650 are copied to the processor (1) program cache memory 612. Accordingly, the processor (1) program codes stored in the external RAM 650 cannot be rewritten. As a result, apart of the external RAM 650 is occupied for storing the program codes. In this case, it is necessary to store all the program codes that cannot be stored in the internal program memory 613, in the external RAM 650. This results in a problem that a free space of the external RAM 650 is reduced, and the external RAM capacity cannot be reduced to a predetermined capacity or smaller.